Multiple clock signals generated with different respective phases but with the same shared frequency are often collectively referred to as a multi-phase signal. One particular example of a multi-phase signal is a multi-phase clock (or multi-phase clock signal). Multi-phase clocks are used in many applications to improve, for example, the accuracy of timing while maintaining the same frequency. As an example, the nominal phase offset between each of the four constituent clock signals of a multi-phase quadrature clock is 90 degrees; that is, a first one of the clock signals of the multi-phase quadrature clock is nominally taken to have zero degree phase, the second one of the clock signals of the multi-phase quadrature clock has a nominal 90 degree phase offset relative to the first one of the clock signals, the third one of the clock signals of the multi-phase quadrature clock has a nominal 90 degree phase offset relative to the second one of the clock signals (and hence a 180 degree phase offset relative to the first one of the clock signals), and the fourth one of the clock signals of the multi-phase quadrature clock has a nominal 90 degree phase offset relative to the third one of the clock signals (and hence a 270 degree phase offset relative to the first one of the clock signals). As another example, the phase offset between the two clock signals of a multi-phase differential clock is nominally 180 degrees.
A clock and data recovery (CDR) circuit or system is one common example of a circuit or system that generally uses a multi-phase clock to avoid operating at the frequency of the incoming data. That is, by sampling the incoming data using a multi-phase clock, the frequency of the clock doesn't have to match the frequency of the incoming data (e.g., each constituent clock signal of an n-phase clock may have 1/nth or less the frequency of the incoming data). CDR circuits are generally used to sample an incoming data signal, extract the clock from the incoming data signal, and retime the sampled data. A phase-locked loop (PLL)-based CDR circuit is a conventional type of CDR circuit. By way of example, in a conventional PLL-based CDR, a phase detector compares the phase between input data bits from a serial input data stream and a clock signal from a voltage-controlled oscillator (VCO). In response to the phase difference between the input data and the clock, the phase detector generates signals that will ultimately result in an increase (e.g., as a result of an “UP” signal) or decrease (e.g., as a result of a “DN” signal) of the frequency or phase of the clock signal generated by the VCO so as to match the frequency of the incoming data. A charge pump drives a current to or from a loop filter according to the UP and DN signals, respectively. The loop filter generates a control voltage VCTRL for the VCO based on the current driven to or from the loop filter based on the UP and DN signals. The loop just described serves as a feedback control system that tracks the phase of input data stream with the phase of the clock that the loop generates. The dynamics of the loop are generally determined by the open loop gain and the location of open loop zeroes and poles (predominantly in the loop filter).
In high-performance applications, a VCO is typically built around an LC tank that consists of an inductor and a capacitor arranged in a parallel configuration. This type of VCO is commonly referred to as an LCVCO. LCVCOs can be configured for fixed frequency and variable frequency operation, the latter being achieved with the use of a varactor (a variable capacitor). LCVCOs generally include two main stages: a gain stage and the LC tank. Furthermore, LCVCOs generally have excellent phase noise and jitter performance at high frequencies.
However, one problem with generating multiple clock phases with an LCVCO is that one LC tank can generate only two complementary clock phases (e.g., zero and 180 degrees), and hence, two LC tanks are typically coupled to one another to produce a desired phase shift in the clock signals generated by one of the two coupled LCVCOs (e.g., 90 degrees in the case of a quadrature clock). One example of an application in which a non-90 degree phase offset is desired or required is in a phase adjust specification in an optical communication system in which the data sampling phases are required to be user-controlled with respect to the center of the eye of the data.